High-Speed and High-efficient Modulo (2n-3) Multipliers
نویسندگان
چکیده
In this paper, an algorithm for designing efficient modulo 2n-3 multipliers is proposed. With this algorithm, we can design the fastest among all known modulo 2n-3 multipliers by applying some simple correction terms. Implemented using 90nm CMOS process technology, the proposed modulo 2n-3 multiplier can improve the current state of the art by 3.9% on the average in terms of area and 10.536.4% in terms of performance delay. KEYWORD-Residue Number System (RNS), Modulo, Multiplier
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تاریخ انتشار 2015